74LVC1G125GW,125 – Buffer / Line Driver, 74LVC1G125, 1.65 V to 5.5 V, TSSOP-5

The 74LVC1G125GW,125 is a non-inverting buffer/Line Driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A high-level at pin OE causes the output to assume a high-impedance off-state. The input can be driven from either 3.3 or 5V devices. This feature allows the use of this device in a mixed 3.3 and 5V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

• High noise immunity
• ±24mA Output drive (VCC=3.0V)
• CMOS Low power consumption
• Inputs accept voltages up to 5V
• Latch-up performance exceeds 250mA
• Direct interface with TTL levels
• Complies with JEDEC standard

Applications

Power Management

ESD sensitive device, take proper precaution while handling the device.